1. Field of the Disclosure
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the manufacture of field effect transistors in complex circuits including memory areas, for instance in the form of a cache memory of a CPU.
2. Description of the Related Art
Integrated circuits comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein transistor elements represent one of the major semiconductor elements in the integrated circuits. Hence, the characteristics of the individual transistors significantly affect overall performance of the complete integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
On the other hand, the drive current capability of MOS transistors also depends on the transistor width, i.e., the extension of the transistor in a direction perpendicular to the current flow direction, so that the gate length, and thus the channel length, in combination with the transistor width, are dominant geometric parameters which substantially determine the overall transistor characteristics, in combination with “transistor internal” parameters, such as overall charge carrier mobility, threshold voltage, i.e., a voltage at which a conductive channel forms below the gate insulation layer upon applying a control signal to the gate electrode, and the like. On the basis of field effect transistors, such as N-channel transistors and/or P-channel transistors, more complex circuit components may be created, depending on the overall circuit layout. For instance, storage elements in the form of registers, static RAM (random access memory), may represent important components of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements have a significant influence on the overall performance of the CPU. Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells. Typically, a dynamic RAM cell comprises a storage capacitor and a single transistor, wherein, however, a complex memory management system is required to periodically refresh the charge stored in the storage capacitors, which may otherwise be lost due to unavoidable leakage currents. Although the bit density of dynamic RAM devices may be very high, charge has to be transferred from and to the storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption compared to static RAM cells. Thus, static RAM cells may be advantageously used as high speed memory with moderately high power consumption, thereby, however, requiring a plurality of transistor elements so as to allow the reliable storage of an information bit.
FIG. 1a schematically illustrates a circuit diagram of a static RAM cell 150 in a configuration as may typically be used in modern integrated circuits. The cell 150 comprises a storage element 151, which may include two inversely coupled inverters 152A, 152B, each of which may include a couple of transistors 10A, 100C. For example, in a CMOS device, the transistors 100A, 100C may represent an N-channel transistor and a P-channel transistor, respectively, while in other cases transistors of the same conductivity type, such as N-channel transistors, may be used for both the transistor 100A and 100C. A corresponding arrangement of N-channel transistors for the upper transistors 100C is illustrated at the right-hand side of FIG. 1a. Moreover, respective pass transistors 100B may typically be provided to allow a connection to the bit cell 151 for read and write operations, during which the pass transistors 100B may connect the bit cell 151 to corresponding bit lines (not shown), while the gate electrodes of the pass transistors 100B may represent word lines of the memory cell 150. Thus, as illustrated in FIG. 1a, six transistors may be required to store one bit of information, thereby providing a reduced bit density for the benefit of a moderately high operating speed of the memory cell 150, as previously explained. Depending on the overall design strategy, the memory cell 150 may require the various transistor elements 100A, 100B, 100C to have different characteristics with respect to drive current capability in order to provide reliable operational behavior during read and write operations. For example, in many design strategies, the transistor elements are provided with minimum transistor length, wherein the drive current capability of the transistors 100A, which may also be referred to as pull-down transistors, may be selected to be significantly higher compared to the drive current capability of the pass transistors 100B, which may be accomplished by appropriately adjusting the respective transistor width dimensions for the given desired minimum transistor length.
FIG. 1b schematically illustrates a top view of a portion of the memory cell 150 as a hardware configuration in the form of a semiconductor device. As illustrated, the device 150 comprises a silicon-based semiconductor layer 103C, in which an active region 103 is defined, for instance, by providing a respective isolation structure 102 that laterally encloses the active region 103, thereby defining the geometric shape and size of the transistors 100A, 100B. As illustrated, the transistors 100A, 100B may be formed in and above the same active region 103 since both transistors may have the same conductivity type and may be connected via a common node, as is for instance illustrated as nodes 153A, 153B in FIG. 1a. As previously explained, the transistors 100A, 100B, i.e., the pull-down transistor and the pass transistor, may have substantially the same length so that respective gate electrodes 106 may have substantially the same length 106L, whereas a transistor width 103A of the pull-down transistor 100A may be greater compared to a transistor width 103B of the pass transistor 100B, in order to establish the different current capabilities of these transistors.
FIG. 1c schematically illustrates a cross-sectional view taken along the line 1c of FIG. 1b. As illustrated, the device 150 comprises a substrate 101 which may typically be provided in the form of a silicon substrate, possibly in combination with a buried insulating layer (not shown) if an SOI (silicon on insulator) is considered. Above the substrate 101 and a possible buried insulating layer the semiconductor layer 103c in the form of a silicon layer is provided, in which the isolation structure 102 may be formed according to the desired shape so as to define the active region 103 according to the configuration as shown in FIG. 1b. That is, the active region 103 has the width 103a in the transistor 100a and has the width 103b in the transistor 100b. In this respect, an active semiconductor region is to be understood as a semiconductor region having an appropriate dopant concentration and profile so as to form one or more transistor elements in and above the active region, which have the same conductivity type. For example, the active region 103 may be provided in the form of a lightly p-doped semiconductor material, for instance in the form of a p-well, when the semiconductor layer 103c may extend down to a depth that is significantly greater than the depth dimension of the transistors 100a, 100b, when the transistors 100a, 100b may represent n-channel transistors. Similarly, the active region 103 may represent a basically n-doped region when the transistors 100a, 100b represent p-channel transistors. Furthermore, in the manufacturing stage shown in FIG. 1c, the transistors 100a, 100b may comprise the gate electrode 106, for instance in the form of a polysilicon material, which is separated from a channel region 109 by a gate insulation layer 108. Furthermore, depending on the overall process strategy, a sidewall spacer structure 107 may be formed on sidewalls of the gate electrodes 106. Additionally, drain and source regions 110 may be formed in the active region 103 and may connect the transistors 100a, 100b. Typically, metal silicide regions 111 are provided in the gate electrode 106 and an upper portion of the drain and source regions 110, so as to reduce contact resistance of these areas.
FIG. 1c schematically illustrates a cross-sectional view taken along the line 1c of FIG. 1b. As illustrated, the device 150 comprises a substrate 101 which may typically be provided in the form of a silicon substrate, possibly in combination with a buried insulating layer (not shown) if a silicon-on-insulator (SOI) is considered. Above the substrate 101 and a possible buried insulating layer, the semiconductor layer 103C, in the form of a silicon layer, is provided, in which the isolation structure 102 may be formed according to the desired shape to define the active region 103 according to the configuration as shown in FIG. 1b. That is, the active region 103 has the width 103A in the transistor 100A and has the width 103B in the transistor 100B. In this respect, an active semiconductor region is to be understood as a semiconductor region having an appropriate dopant concentration and profile so as to form one or more transistor elements in and above the active region, which have the same conductivity type. For example, the active region 103 may be provided in the form of a lightly P-doped semiconductor material, for instance in the form of a P-well, when the semiconductor layer 103C may extend down to a depth that is significantly greater than the depth dimension of the transistors 100A, 100B, when the transistors 100A, 100B may represent N-channel transistors. Similarly, the active region 103 may represent a basically N-doped region when the transistors 100A, 100B represent P-channel transistors. Furthermore, in the manufacturing stage shown in FIG. 1c, the transistors 10A, 100B may comprise the gate electrode 106, for instance in the form of a polysilicon material, which is separated from a channel region 109 by a gate insulation layer 108. Furthermore, depending on the overall process strategy, a sidewall spacer structure 107 may be formed on sidewalls of the gate electrodes 106. Additionally, drain and source regions 110 may be formed in the active region 103 and may connect the transistors 100A, 100B. Typically, metal silicide regions 111 are provided in the gate electrode 106 and an upper portion of the drain and source regions 110 to reduce contact resistance of these areas.
The device 150 is typically formed on the basis of the following processes. First, the isolation structure 102 may be formed, for instance as a shallow trench isolation, by etching respective openings into the semiconductor layer 103C down to a specific depth, which may even extend to a buried insulating layer, if provided. Thereafter, the corresponding openings may be filled with an insulating material by deposition and oxidation processes, followed by a planarization such as chemical mechanical polishing (CMP) and the like. During the process sequence for the isolation structure 102, advanced lithography techniques may have to be used in order to form a corresponding etch mask, which substantially corresponds to the shape of the active region 103, which requires the definition of a moderately narrow trench to obtain the desired reduced width 103B of the transistor 100B. Thereafter, the basic doping in the active region 103 may be provided by performing respective implantation sequences, which may also include sophisticated implantation techniques for introducing dopants for defining the channel doping and the like. Next, the gate insulation layers 108 and the gate electrodes 106 may be formed by depositing, oxidizing and the like an appropriate material for the gate insulation layer 106, followed by the deposition of an appropriate gate electrode material, such as polysilicon. Subsequently, the material layers are patterned by using advanced lithography and etch techniques, during which the actual length 106L of the gate electrodes 106 may be adjusted, thereby requiring extremely advanced process techniques to obtain a gate length of approximately 50 nm and less. Next, a part of the drain and source regions 110 may be formed by implanting appropriate dopant species, followed by the formation of the spacer structure 107, or at least a portion thereof, followed by a subsequent implantation process for defining the deep drain and source areas, wherein a corresponding implantation sequence may be repeated on the basis of an additional spacer structure if sophisticated lateral concentration profiles may be required in the drain and source regions 110. Thereafter, appropriate anneal processes may be performed to re-crystallize implantation-induced damage in the active region 103 and also to activate the dopant species in the drain and source areas 110.
It should be appreciated that, for a reduced gate length in the above-defined range, the sophisticated geometric configuration of the active region 103 may result in process non-uniformities, for instance during the deposition and etching of a spacer material for forming the sidewall spacer 107. Typically, the spacer structure 107 is formed by depositing an appropriate material, for instance a silicon dioxide liner (not shown) followed by a silicon nitride material, which may be subsequently selectively etched with respect to the silicon dioxide liner on the basis of well-established anisotropic etch recipes. However, at areas indicated as 112 in FIG. 1b, irregularities may be observed which may even be increased due to respective non-uniformities created during previously performed lithography processes, such as the lithography process for patterning the gate electrodes 106 and the like. Consequently, the areas 112 may have a significant influence on the further processing of the device 150, which may finally result in a non-predictable behavior of the transistor 100B and thus the overall memory cell 150.
One prominent failure mechanism is associated with shorts caused by nickel silicide leakage paths. That is, during the further processing, the metal silicide regions 111 may be formed by depositing a refractory metal, such as nickel, which may then be treated to react with the underlying silicon material, wherein, typically, the isolation structure 102 and the spacer structure 107 may substantially suppress the creation of a highly conductive metal silicide. However, due to the previously generated irregularities, respective leakage paths or even short circuits may be created, which are believed to be caused by corresponding diffusion paths created by the previously generated irregularities. Thus, nickel may migrate along the diffusion paths and may form an electrical connection between per se isolated areas, such as the gate electrode 106 and the active region 103, thereby undesirably influencing the final drive current capability of the transistor 100B, which may result in a less stable and less reliable operation of the memory cell 150, or even cause a complete failure of the memory cell 150, thereby significantly contributing to yield loss of sophisticated semiconductor devices including static RAM areas.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.